Datasheet

UCC28250

www.ti.com

SLUSA29C –APRIL 2010– REVISED JULY 2011

APPLICATION INFORMATION

The UCC28250 is a high performance PWM controller with advanced synchronous rectifier outputs and is ideally

suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal pre-biased start up

control loop working in conjunction with a primary-side voltage loop achieves monotonic pre-biased start up for

either primary-side or secondary-side control applications. The UCC28250 architecture allows either voltage

mode or current mode control.

Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line

transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault

conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.

With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and over

temperature protection can be implemented. The UCC28250 allows individual programming of dead time

between primary-side switch and secondary-side SRs, in order to allow optimal power stage design. Dead time

can also be reduced to zero, and this allows optimal system configuration considering the delays on the gate

driver stage. The UCC28250 also provides complete system level protection functions, including UVLO, thermal

shut down and over voltage, over current protection.

Error Amplifier and PWM Generation

The UCC28250 includes a high performance internal error amplifier with low input offset, high source/sink current

capability and high gain bandwidth (typical 3.5 MHz). The reference of the error amplifier (REF/EA+ pin) is set

externally to support flexible trimming of the voltage loop, and to make the controller flexible for both primary

side, as well as secondary-side control. The extra positive input for the error amplifier is the SS pin which is used

to externally program the soft-start time of the converter’s output.

During steady state operation, the primary switch duty cycle, D, is generated based on the external ramp on

RAMP/CS pin and the COMP pin voltage. A higher COMP pin voltage results in a larger duty cycle. The

secondary-side SR duty cycle is SR_D = (1-D), complementary to the primary-side duty cycle, without

considering the dead time between primary-side switch and secondary-side SR. The primary outputs begin to

switch when COMP pin voltage is above the 350 mV internal offset. The synchronous rectifier outputs only switch

after COMP pin voltage is above 550 mV internal offset. According to the internal logic, the minimum pulse width

for the primary-side OUTA and OUTB is typically 100 ns.

During soft start, the primary-side switch duty cycle is generated based on the external ramp on RAMP/CS pin

and the COMP pin voltage. However, the duty cycle of secondary-side SR is generated based on an internal

ramp and the COMP pin voltage. When the converter is controlled on the primary side, an internal ramp is a

fixed ramp with 3-V peak voltage. When the converter is controlled on secondary side, an internal ramp is

generated based on the internal pre-biased start-up loop. An internal pre-biased start-up loop modifies the SR

duty cycle during soft start to achieve the optimal pre-biased start-up performance.

After the SS pin reaches 2.9 V, the pre-biased start-up control loop is disabled. The secondary-side SR

instantaneously changes into its steady state value as complementary to the primary-side duty cycle.

Product Folder Link(s): UCC28250