Datasheet

OC(delay)
HICC
T 75 A
C
0.6 V
´ m
=
0.3V
0.6V
2.4V
HICC
t
t
4V
SS
OUTA
OUTB
Normal OC Normal OC Hiccup Soft Start
T
OCdealy
T
HICC
OC(delay) HICC
0.6 V
T C
75 A
= ´
m
HICC HICC
2.4 V 0.3 V
T C
2.7 A
-
= ´
m
UCC28250
www.ti.com SLUSA29C –APRIL 2010– REVISED JULY 2011
HICC (10/17)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by an
external capacitor C
HICC
from HICC pin to ground, as shown in Figure 15. Once all four outputs are shutdown,
controller goes into hiccup cycle which is about 100 times of the cycle-by-cycle current limit shut-down delay
time. A 1-mA internal current source charges HICC pin up to 2.4 V, then the HICC pin is discharged by a 2.7-µA
internal current source to generate long hiccup restart time until HICC reaches 0.3 V. Based on the system
requirement, once the cycle-by-cycle current limit delay time T
OC(delay)
is selected, the HICC pin capacitor C
HICC
can be selected based on the equation
(13)
Figure 16. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
As shown in Figure 16, cycle-by-cycle current limiting shut-down delay time is:
(14)
And hiccup-restart-time T
HICC
is equal to:
(15)
As soon as the outputs are shut-down, the SS pin is pulled to ground internally until the hiccup restart timer is
reset after time duration T
HICC
.
Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): UCC28250