Datasheet

UCC28250
SLUSA29C –APRIL 2010– REVISED JULY 2011 www.ti.com
ORDERING INFORMATION
TEMPERATURE RANGE
PACKAGE TAPE AND REEL QTY PART NUMBER
T
A
= T
J
250 UCC28250RGPT
Plastic 20-pin QFN (RGP)
3000 UCC28250RGPR
-40°C to 125°C
250 UCC28250PWT
Plastic 20-pin TSSOP (PW)
3000 UCC28250PWR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range
(1)(2)
(unless otherwise noted)
PARAMETER VALUE UNIT
VDD
(3)
Input supply voltage -0.3 to 20.0
OUTA, OUTB, SRA and SRB -0.3 to VDD + 0.3
COMP -0.3 to VREF + 0.3
Input voltages on SS and EN -0.3 to 5.5
Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA- -0.3 to 3.6 V
Input voltage on RAMP/CS -0.3 to 4.3
Output voltage on VREF -0.3 to 3.6
HBM 3 k
ESD rating
CDM 2 k
Lead temperature (soldering 10 sec) PW package 300 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
THERMAL INFORMATION
UCC28250 UCC28250
THERMAL METRIC RGP PW
(1)
UNITS
20 PINS 20 PINS
θ
JA
126 with hot spot, 60.3 with hot spot,
Junction-to-ambient thermal resistance
(2)
104 without hot spot 39.3 without hot spot
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
31.5
°C/W
θ
JB
Junction-to-board thermal resistance
(4)
55.8
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(5)
0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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