Datasheet

 
SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009
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APPLICATION INFORMATION
Slope Compensation
The slope compensation circuit in the UCC28220/1 operates on a cycle-by-cycle basis. The two channels have
separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing
is unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that
channel’s output is off. At the beginning of the PWM cycle, a current is mirrored off the SLOPE pin into the
capacitor, developing an independent ramp. Since the two channel’s ramps will start when the channel’s output
changes from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltages
on the current sense pins, CS1 and CS2 and the result forms an input to the PWM comparators.
PWM
CS1
(4)
+
−
REF
CTRL
(8)
+
SLOPE
(5)
C_SC
OUT 1
TO RESET
of
PWM LATCH
ON OFF
2.5/(16.6*R_SLOPE)=I_SC
R_SLOPE
0.5V
10 pF
S1
S2
Figure 4. Slope Compensation Detail for Channel 1. Duplicate Matched Circuitry Exists for Channel 2.
To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope
to each of the current sense signals prior to being applied to the PWM comparator’s input.