Datasheet

 
SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009
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APPLICATION INFORMATION
VDD
HV JFET
OUTx
GATE DRV
ON
0V
8 − 14 V
13 V
10 V
OFF
ON
OFF
8 V (UVLO off)
13 V
NORMAL OPERATION
Figure 3. JFET Device Operation with VDD Voltage
Soft-Start
A current is forced out of the SS pin, equal to 3/7 of the current set by R
CHG
, to provide a controlled ramp voltage.
The current set by the R
CHG
resistor is equal to 2.5 V divided by R
CHG
. This ramp voltage overrides the
commanded duty cycle on the CTRL pin, allowing a controlled start-up. Assuming the UCC28221 is biased on
the primary side, the soft start should be quite quick to allow the secondary bias to be generated and the
secondary side control can then take over. Once the soft-start time interval is complete, a closed loop soft-start
on the secondary side can be executed.
ISS +
3
7
2.5
R
CHG
where,
ISS = current which is sourced out of the SS pin during the soft-start time − [Amps]
Current Sense
The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation ramps
added to them before being compared to the control voltage at the input of the PMW comparators. The
amplitude of the current sense signal at full load should be selected such that it is very close to the maximum
control voltage in order to limit the peak output current during short circuit operation.
Output Drivers
The UCC28220/1 is intended to interface with the UCC27323/4/5 family of MOSFET drivers. As such, the output
drive capability is low, effectively 100 Ω and the driver outputs swing between GND and REF.
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