Datasheet

 
SLUS544E − SEPTEMBER 2003 − REVISED MARCH 2009
11
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APPLICATION INFORMATION
Reference
For improved noise immunity it is recommended that the reference pin, REF, be bypassed with a minimum of
0.1uF of capacitance to GND.
Oscillator Operation and Maximum Duty Cycle Setpoint
The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is
programmable over a 200 kHz to 2MHz frequency range with 20% to 80% maximum duty cycle range. Both the
dead time and the frequency of the oscillator are divided by 2 to generate the PWM clock and off-time information
for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty cycle at
each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output.
The design equations for the oscillator and maximum duty cycle set point are given by:
F
OSC
+ 2 F
OUT
D
MAX(osc)
+ 1 * 2
ǒ
1 * D
MAX(out)
Ǔ
R
CHG
+ K
OSC
D
MAX(osc)
F
OSC
R
DISCHG
+ K
OSC
ǒ
1 * D
MAX(osc)
Ǔ
F
OSC
Where:
• K
OSC
= 2.04 x 10
10
[Ω/s]
• F
OUT
= Switching frequency at the outputs of the chip [Hz]
• D
MAX(out)
= Maximum duty cycle limit at the outputs of the chip
• D
MAX(osc)
= Maximum duty cycle of the Oscillator for the desired maximum duty cycle at the outputs
• F
OSC
= Oscillator frequency for desired output frequency [Hz]
• R
CHG
= External oscillator resistor which sets the charge current − [Ω]
• R
DISCHG
= External oscillator resistor which sets the discharge current − [Ω]
Start-Up JFET Section
A 110-V start-up JFET is included to start the device from a wide range (36 V−75 V) telecom input source. When
VDD is lower than 13 V the JFET is on, behaving as a current source charging the bias capacitors on VDD and
supplying current to the device. In this way, the VDD bypass capacitors are charged to 13 V where the outputs
start switching and the JFET is turned off. To enable a constant bias supply to the device during a pulse skipping
condition, the JFET is turned back on whenever VDD decreases below 10 V and the outputs are not switching.
Thus, the current from the JFET can overcome the internal bias currents, as long as the device is not actively
switching the output drivers. See Figure 2 below for a graphical representation of the JFET/VDD operation. The
UCC28220 does not contain an internal JFET and has a startup threshold of 10 V which makes it capable of
directly operating off a 12 V dc bus
(5)
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