Datasheet
R +
V
RMS
0.9
I
C
Capacitor Ripple Reduction
UDG-97130-1
L
IN
i
D1
i
Q2
D1 Q2
V
BST
C
BST
i
CB
Q1
LOAD
I
L
UCC2817-EP
UCC2818-EP
SLUS716 – DECEMBER 2008 ...........................................................................................................................................................................................
www.ti.com
Where:
I
C
= Charge current
C = Total capacitance at the V
CC
pin
Δ V = UVLO threshold
Δ t = Allowed start-up time
Assuming a 1-s allowed start-up time, a 16-V UVLO threshold, and a total V
CC
capacitance of 100 µ F, a resistor
value of 51 k Ω is required at a low line input voltage of 85 V
RMS
. The IC start-up current is sufficiently small as to
be ignored in sizing the start-up resistor.
For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits
to synchronizing the two converters. In addition to the usual advantages, such as noise reduction and stability,
proper synchronization can significantly reduce the ripple currents in the boost circuit output capacitor. Figure 5
shows the impact of proper synchronization by showing a PFC boost converter together with the simplified input
stage of a forward converter. The capacitor current during a single switching cycle depends on the status of the
switches Q1 and Q2 and is shown in Figure 6 . With a synchronization scheme that maintains conventional
trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current
cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving
this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the
boost converter leading edge is pulse width modulated, while the forward converter is modulated with traditional
trailing-edge PWM. The UCC2817 is designed as a leading edge modulator with easy synchronization to the
downstream converter to facilitate this advantage. Table 1 compares the I
CB(rms)
for D1/Q2 synchronization as
offered by UCC2817, versus the I
CB(rms)
for the other extreme of synchronizing the turnon of Q1 and Q2 for a
200-W power system with a V
BST
of 385 V.
Figure 5. Simplified Representation of a Two-Stage PFC Power Supply
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