Datasheet

R
VFF
+
1.4 V
V
IN(min)
0.9
2 R
IAC
[ 30 kW
1.5 %
66 %
+ 0.022
f
P
= 120 Hz × 0.022 ≈ 2.6 Hz
C
VFF
+
1
2 p R
VFF
f
P
[ 2.2 mF
I
MOUT(max)
+
I
IAC
@V
IN(min)
ǒ
V
VAOUT(max)
* 1 V
Ǔ
K V
VFF
2
(min)
UCC2817-EP
UCC2818-EP
SLUS716 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
Where:
K = Constant typically equal to 1/V
The Electrical Characteristics table covers all the required operating conditions for designing with the multiplier.
Additionally, curves in Figure 10 , Figure 11 , and Figure 12 provide typical multiplier characteristics over its entire
operating range.
The I
IAC
signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin
of the UCC2817 and UCC2818. This resistor R
IAC
is sized to give the maximum I
IAC
current at high line. For the
UCC2817 and UCC2818, the maximum I
IAC
current is about 500 µ A. A higher current than this can drive the
multiplier out of its linear range. A smaller current level is functional, but noise can become an issue, especially
at low input line. Assuming a universal line operation of 85 V
RMS
to 265 V
RMS
gives a R
IAC
value of 750 k Ω ,
because of voltage-rating constraints of a standard 1/4-W resistor, use a combination of lower-value resistors
connected in series to give the required resistance and distribute the high voltage amongst the resistors. For this
design example, two 383-k Ω resistors were used in series.
The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage
feed-forward signal proportional to line voltage. The VFF voltage is used to keep the power-stage gain constant,
and to provide input power limiting.See the TI application report SLUA196 for detailed explanation on how the
VFF pin provides power limiting. The following equation can be used to size the VFF resistor R
VFF
to provide
power limiting where V
IN(min)
is the minimum RMS input voltage, and R
IAC
is the total resistance connected
between the IAC pin and the rectified line voltage.
Because the VFF voltage is generated from line voltage, it needs to be adequately filtered to reduce THD caused
by the 120-Hz rectified line voltage. Refer to Unitrode Power-Supply Design Seminar, SEM-700 Topic 7
( Optimizing the Design of a High Power Factor Preregulator). A single pole filter was adequate for this design.
Assuming that an allocation of 1.5% total harmonic distortion from this input is allowed, and that the second
harmonic ripple is 66% of the input ac line voltage, the amount of attenuation required by this filter is:
A ripple frequency (f
R
) of 120 Hz and an attenuation of 0.022 requires that the pole of the filter (f
P
) be placed at:
The following equation can be used to select the filter capacitor C
VFF
required to produce the desired low-pass
filter.
The R
MOUT
resistor is sized to match the maximum current through the sense resistor to the maximum multiplier
current. The maximum multiplier current, or I
MOUT(max)
, can be determined by the equation:
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