Datasheet

UCC28070
www.ti.com SLUS794E –NOVEMBER 2007–REVISED APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range −40°C < T
A
< 125°C, T
J
= T
A
, VCC = 12 V, GND = 0 V, R
RT
= 75 kΩ, R
DMX
= 68.1
kΩ, R
RDM
= R
SYN
= 100 kΩ, C
CDR
= 2.2 nF, C
SS
= C
VREF
= 0.1 μF, C
VCC
= 1 μF, I
VREF
= 0 mA (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Clock Synchronization
V
CDR
SYNC enable threshold Measured at CDR (rising) 5 5.25 V
V
CDR
= 6 V, Measured from RDM (rising) to
SYNC propagation delay 50 100 ns
GDx (rising)
SYNC threshold (Rising) V
CDR
= 6 V, Measured at RDM 1.2 1.5
V
SYNC threshold (Falling) V
CDR
= 6 V, Measured at RDM 0.4 0.7
Positive pulse width 0.2 μs
SYNC pulses
Maximum duty cycle
(2)
50 %
Voltage Amplifier
VSENSE voltage In regulation, T
A
= 25°C 2.97 3 3.03
V
VSENSE voltage In regulation 2.94 3 3.06
VSENSE input bias current In regulation 250 500 nA
VAO high voltage VSENSE = 2.9 V 4.8 5 5.2
V
VAO low voltage VSENSE = 3.1 V 0.05 0.50
g
MV
VAO transconductance 2.8 V < VSENSE < 3.2 V, VAO = 3 V 70 μS
VAO sink current, overdriven limit VSENSE = 3.5 V, VAO = 3 V 30
VAO source current, overdriven VSENSE = 2.5 V, VAO = 3 V, SS = 3 V −30
μA
VAO source current,
VSENSE = 2.5 V, VAO = 3 V −130
overdriven limit + I
SRC
Measured as VSENSE (falling) / VSENSE
Slew-rate correction threshold 92 93 95 %
(regulation)
Slew-rate correction hysteresis Measured at VSENSE (rising) 3 9 mV
Measured at VAO, in addition to VAO
I
SRC
Slew-rate correction current −100 μA
source current.
Slew-rate correction enable threshold Measured at SS (rising) 4 V
VAO discharge current VSENSE = 0.5 V, VAO = 1 V 10 μA
Soft Start
I
SS
SS source current VSENSE = 0.9 V, SS = 1 V −10 μA
Adaptive source current VSENSE = 2.0 V, SS = 1 V −1.5 -2.5 mA
Adaptive SS disable Measured as VSENSE – SS -30 0 30 mV
SS sink current VSENSE = 0.5 V, SS = 0.2 V 0.5 0.9 mA
(2) Due to the influence of the synchronization pulse width on the programmability of the maximum PWM switching duty cycle (D
MAX
) it is
recommended to minimize the synchronization signal's duty cycle.
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