Datasheet

( ) ( )
( )
RS D RSER LK
on max ON max
V t V V V V
m
= ´ + + +
Z
RST
R
RST
D D
R
RST
C
RST
UCC28070
www.ti.com SLUS794E –NOVEMBER 2007–REVISED APRIL 2011
It is vital that the CT has plenty of Vμs design-margin to accommodate various special situations where there to
be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current
limiting.
Maximum Vμs(on) can be estimated by:
(34)
where all factors are maximized to account for worst-case transient conditions and t
ON(max)
occurs during the
lowest dither frequency when frequency dithering is enabled. For design margin, a CT rating of ~5*Vμs(on)max
or higher is suggested. The contribution of V
RS
varies directly with the line current. However, V
D
may have a
significant voltage even at near-zero current, so substantial Vμs(on) may accrue at the zero-crossings where the
duty-cycle is maximum. V
RSER
is the least contributor, and often can be neglected if R
SER
<<R
S
. V
LK
is developed
by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given
the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the
built-up Vμs across L
M
during the on-time is removed during the fall-time at the end of the duty-cycle, leaving a
lower net Vμs(on) to be reset during the off-time. Nevertheless, the CT must, at the very minimum, be capable of
sustaining the full internal Vμs(on)max built up until the moment of turn-off within a switching period.
Vμs(off) may be generated with a resistor or zener diode, using the i
M
as bias current.
Figure 25. Possible Reset Networks
In order to accommodate various CT circuit designs and prevent the potentially destructive result due to CT
saturation, the UCC28070’s maximum duty-cycle needs to be programmed such that the resulting minimum
off-time accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of
the data sheet for more information on sizing R
DMX
) Be aware that excessive C
d
in the CT can interfere with
effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT
self-resonant frequency. A higher turns-ratio results in higher C
d
[3], so a trade-off between N
CT
and D
MAX
must
be made.
The selected turns-ratio also affects L
M
and L
LK
, which vary proportionally to the square of the turns. Higher L
M
is
good, while higher L
LK
is not. If the voltage across L
M
during the on-time is assumed to be constant (which it is
not, but close enough to simplify) then the magnetizing current is an increasing ramp.
This upward ramping current subtracts from i
RS
, which affects V
CSx
especially heavily at the zero-crossings and
light loads, as stated earlier. With a reduced peak at V
CSx
, the current synthesizer starts the down-slope at a
lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these
conditions. If low input current distortion at very light loads is required, special mitigation methods may need to
be developed to accomplish that goal.
Copyright © 2007–2011, Texas Instruments Incorporated 35