Datasheet

0
2
2
avg Cout avg
pk
avg avg LF
Pin X Pin
v
Vout Vout f Coutp
´
= =
´ ´ ´
2
3 2
64 2
LF
rd avg LF
OV ( f )
mv R avg
k mV Vout f Cout
Z
g k Pin
p´ ´ ´ ´
=
´ ´
2
3 2
64 2
mv R avg
rd avg LF
g k Pin
Cpv
k mV Vout ( f ) Coutp
´ ´
=
´ ´ ´ ´
( )
1
avg Cout
VXO BST VEA R mv Cpv R
VAO avg
Pin X
Tv( f ) G G k g X k
V Vout
æ ö
´
= ´ ´ = ´ ´ ´ =
ç ÷
ç ÷
D ´
è ø
( )
2
2
2
mv R avg
VXO
VAO avg
g k Pin
f
V Vout Cpv Coutp
´ ´
=
D ´ ´ ´ ´
1
2
VXO
Rzv
f Cpvp
=
´
10
10
2
VXO
Czv Cpv
f Rzvp
= » ´
´
UCC28070
SLUS794E – NOVEMBER 2007–REVISED APRIL 2011 www.ti.com
The output capacitor maximum low-frequency zero-to-peak ripple voltage is closely approximated by:
(27)
where P
IN(avg)
is the total maximum input power of the interleaved-PFC pre-regulator, V
OUT(avg)
is the average
output voltage and C
OUT
is the output capacitance.
V
SENSEpk
= v
opk
xk
R
, where k
R
is the gain of the resistor-divider network on VSENSE.
Thus, for k
3rd
% of allowable 3rd-harmonic distortion on the input current attributable to the VAO ripple,
(28)
This impedance on VAO is set by a capacitor (Cpv), where C
PV
= 1/( 2πf
2LF
xZ
OV
(f
2LF
)) therefore,
(29)
The voltage-loop unity-gain cross-over frequency (f
VXO
) may now be solved by setting the open-loop gain equal
to 1:
(30)
so, (31)
The “zero-resistor” (R
ZV
) from the zero-placement network of the compensation may now be calculated. Together
with C
PV
, R
ZV
sets a pole right at f
VXO
to obtain 45° phase margin at the cross-over.
Thus, (32)
Finally, a zero is placed at or below f
VXO
/6 with capacitor C
ZV
to provide high gain at dc but with a breakpoint far
enough below f
VXO
so as not to significantly reduce the phase margin. Choosing f
VXO
/10 allows one to
approximate the parallel combination value of C
ZV
and C
PV
as C
ZV
, and solve for C
ZV
simply as:
(33)
By using a spreadsheet or math program, C
ZV
, R
ZV
, and C
PV
may be manipulated to observe their effects on f
VXO
and phase margin and %-contribution to 3rd-harmonic distortion (see note below). Also, phase margin may be
checked as P
IN(avg)
level and system parameter tolerances vary.
NOTE
The percent of 3rd-harmonic distortion calculated in this section represents the
contribution from the f
2LF
voltage ripple on C
OUT
only. Other sources of distortion, such as
the current-sense transformer, the current synthesizer stage, even distorted V
IN
, etc., can
contribute additional 3rd and higher harmonic distortion.
32 Copyright © 2007–2011, Texas Instruments Incorporated