Datasheet

( ) ( )
17 1
VINAC VAO
IMO
VFF
A V V
I
k
m ´ ´ -
=
1 10
OUT (max)
IN (max)
. P
P
h
´
=
1 414
73
IN (max)
IN ( rms ) IN ( pk ) IN( rms )
RMS
P
I , I . I
V
= = ´Thus and
UCC28070
SLUS794E – NOVEMBER 2007–REVISED APRIL 2011 www.ti.com
The multiplier output current I
IMO
for any line and load condition can thus be determined by the equation
(13)
Because the k
VFF
value represents the scaled V
RMS
2
at the center of a level, V
VAO
will adjust slightly upwards or
downwards when VINAC
pk
is either lower or higher than the center of the Q
VFF
voltage range to compensate for
the difference. This is automatically accomplished by the voltage loop control when V
IN
varies, both within a level
and after a transition between levels.
The output of the voltage-error amplifier VAO is clamped at 5.0 V, which represents the maximum PFC output
power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the
maximum input power allowed (and, as a consequence, limits maximum output power).
Unlike a continuous V
FF
situation, where maximum input power is a fixed power at any V
RMS
input, the discrete
Q
VFF
levels permit a variation in maximum input power within limited boundaries as the input V
RMS
varies within
each level.
The lowest maximum power limit occurs at the VINAC voltage of 0.76 V, while the highest maximum power limit
occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold,
keeping in mind that decreasing thresholds are 95% of the increasing threshold values. Below VINAC = 0.76 V,
P
IN
is always less than P
IN(max)
, falling linearly to zero with decreasing input voltage.
For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average)
output power required of the PFC pre-regulator and add some additional percentage to account for line drop-out
recovery power (to recharge C
OUT
while full load power is drawn) such as 10% or 20% of P
OUT(max)
. Then apply
the expected efficiency factor to find the lowest maximum input power allowable:
(14)
At the P
IN(max)
design threshold, V
VINAC
= 0.76 V, hence Q
VFF
= 0.398 and input V
AC
= 73 V
RMS
(accounting for
2-V bridge-rectifier drop) for a nominal 400-V output system.
(15)
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