Datasheet

UCC28070
www.ti.com SLUS794E –NOVEMBER 2007–REVISED APRIL 2011
Linear Multiplier
The multiplier of the UCC28070 generates a reference current which represents the desired wave shape and
proportional amplitude of the ac input current. This current is converted to a reference voltage signal by the R
IMO
resistor, which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier
current is dependent upon the rectified, scaled input voltage V
VINAC
and the voltage-error amplifier output V
VAO
.
The V
VINAC
signal conveys three pieces of information to the multiplier:
1. The overall wave-shape of the input voltage (typically sinusoidal),
2. The instantaneous input voltage magnitude at any point in the line cycle,
3. The rms level of the input voltage.
The V
VAO
signal represents the total output power of the PFC pre-regulator.
A major innovation in the UCC28070 multiplier architecture is the internal quantized V
RMS
feed-forward (Q
VFF
)
circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow
response to transient line variations. A unique circuit algorithm detects the transition of the peak of V
VINAC
through seven thresholds and generates an equivalent VFF level centered within the eight Q
VFF
ranges. The
boundaries of the ranges expand with increasing V
IN
to maintain an approximately equal-percentage delta
between levels. These eight Q
VFF
levels are spaced to accommodate the full “universal” line range of 85 V-265
V
RMS
.
A great benefit of the Q
VFF
architecture is that the fixed k
VFF
factors eliminate any contribution to distortion of the
multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion
components. Furthermore, the Q
VFF
algorithm allows for rapid response to both increasing and decreasing
changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in
the level thresholds help avoid “chattering” between Q
VFF
levels for V
VINAC
voltage peaks near a particular
threshold or containing mild ringing or distortion. The Q
VFF
architecture requires that the input voltage be largely
sinusoidal, and relies on detecting zero-crossings to adjust Q
VFF
downward on decreasing input voltage.
Zero-crossings are defined as V
VINAC
falling below 0.7 V for at least 50 μs typically.
Table 1 reflects the relationship between the various VINAC peak voltages and the corresponding k
VFF
terms for
the multiplier equation.
Table 1. VINAC Peak Voltages
LEVEL V
VINAC
PEAK VOLTAGE k
VFF
(V
2
) V
IN
PEAK VOLTAGE
(1)
8 2.60 V ≤ V
VINAC(pk)
3.857 > 345 V
7 2.25 V ≤ V
VINAC(pk)
< 2.60 V 2.922 300 V to 345 V
6 1.95 V ≤ V
VINAC(pk)
< 2.25 V 2.199 260 V to 300 V
5 1.65 V ≤ V
VINAC(pk)
< 1.95 V 1.604 220 V to 260 V
4 1.40 V ≤ V
VINAC(pk)
< 1.65 V 1.156 187 V to 220 V
3 1.20 V ≤ V
VINAC(pk)
< 1.40 V 0.839 160 V to 187 V
2 1.00 V ≤ V
VINAC(pk)
< 1.20 V 0.600 133 V to 160 V
1 V
VINAC(pk)
≤ 1.00 V 0.398 < 133 V
(1) The V
IN
peak voltage boundary values listed above are calculated based on a 400-V PFC output voltage and the use of a matched
resistor-divider network (k
R
= 3 V/400 V = 0.0075) on VINAC and VSENSE (as required for current synthesis). When V
OUT
is designed
to be higher or lower than 400 V, k
R
= 3 V/V
OUT
, and the V
IN
peak voltage boundary values for each Q
VFF
level adjust to V
VINAC(pk)
/k
R
.
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