Datasheet

Waveform at
CSx input
Synthesized
down-slope
Current Synthesizer
output to CA
( )
( )
( )
( )
10
CT B R
SYN
S
N L H k
R k
R
m´ ´ ´
W =
W
UCC28070
www.ti.com SLUS794E –NOVEMBER 2007–REVISED APRIL 2011
Current Synthesizer
One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that
synchronously monitors the instantaneous inductor current through a combination of on-time sampling and
off-time down-slope emulation.
During the on-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins
respectively via the current transformer network in each output phase. Meanwhile, the continuous monitoring of
the input and output voltage via the VINAC and VSENSE pins permits the UCC28070 to internally recreate the
inductor current’s down-slope during each output’s respective off-time. Through the selection of the RSYNTH
resistor (R
SYN
), based on the equation below, the internal response may be adjusted to accommodate the wide
range of inductances expected across the wide array of applications.
During inrush surge events at power-up and ac drop-out recovery, VSENSE < VINAC, so the synthesized down
slope becomes zero. In this case, the synthesized inductor current will remain above the IMO reference and the
current loop drives the duty cycle to zero. This avoids excessive stress on the MOSFETS during the surge event.
Once VINAC falls below VSENSE the duty cycle increases until steady-state operation resumes.
Figure 19. Inductor Current’s Down Slope
(12)
Variables
• L
B
= Nominal Zero-Bias Boost Inductance (μH),
• R
S
= Sense Resistor (Ω),
• N
CT
= Current-sense Transformer turns ratio,
• k
R
= R
B
/(R
A
+R
B
) = the resistor-divider attenuation at the VSENSE and VINAC pins.
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