Datasheet

( )
B
R
A B
R
k
R R
=
+
UCC28070
www.ti.com SLUS794E –NOVEMBER 2007–REVISED APRIL 2011
Multi-phase Operation
External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can
easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate
phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be
obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be
optimal.) For 4-, 6-, or any 2 x n-phases (where n = the number of UCC28070 controllers), each controller should
receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application
interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation.
Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for
optimal ripple cancellation.
In a multi-phase interleaved system, each current loop is independent and treated separately, however there is
only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO and VAO
signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS,
IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with
a single controller.
Figure 18 illustrates the paralleling of two controllers for a 4-phase 90°-interleaved PFC system.
VSENSE and VINAC Resistor Configuration
The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage
control loop. Thus, a traditional resistor-divider network needs to be sized and connected between the output
capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on
VSENSE.
A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the V
IN
side of the
inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and
current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the
VSENSE network, but it is necessary that the attenuation (k
R
) of the two divider networks be equivalent for
proper PFC operation.
(11)
In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC
inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant
should not exceed 100μs on the VSENSE input to avoid significant delay in the output transient response. The
RC time-constant should also not exceed 100 μs on the VINAC input to avoid degrading of the wave-shape
zero-crossings. Usually, a time constant of 3/f
PWM
is adequate to filter out typical noise on VSENSE and VINAC.
Some design and test iteration may be required to find the optimal amount of filtering required in a particular
application.
VSENSE and VINAC Open Circuit Protection
Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the
event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a “safe”
operating mode.
Copyright © 2007–2011, Texas Instruments Incorporated 19