Datasheet

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SYNC

PWM

f =

( )

15000

1 1W = ´

SYNC

R k .

f kHz

= ´

SYNC SYNC SYNC

D t f

( ) ( )

15000

2 1

æ ö

W = ´ ´ - -

ç ÷

è ø

DMX MAX SYNC

SYNC

R k D D

f ( kHz )

UCC28070

SLUS794E – NOVEMBER 2007–REVISED APRIL 2011

www.ti.com

External Clock Synchronization

The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By

disabling frequency dithering (pulling CDR > 5 V), the UCC28070’s SYNC circuitry is enabled permitting the

internal oscillator to be synchronized with pulses presented on the RDM pin. In order to ensure a precise 180

degree phase shift is maintained between the GDA and GDB outputs, the frequency (f

SYNC

) of the pulses

presented at the RDM pin needs to be at twice the desired f

PWM

. For example, if a 100-kHz switching frequency

is desired, the f

SYNC

should be 200 kHz.

(7)

In order to ensure the internal oscillator does not interfere with the SYNC function, R

should be sized to set the

internal oscillator frequency at least 10% below the f

SYNC

(8)

It must be noted that the PWM modulator gain will be reduced by a factor equivalent to the scaled R

due to a

direct correlation between the PWM ramp current and R

. Adjustments to the current loop gains should be

made accordingly.

It must also be noted that the maximum duty cycle clamp programmability is affected during external

synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the

falling edge of the synchronization pulse. Therefore, the selection of R

DMX

becomes dependent on the

synchronization pulse width (t

SYNC

For use in R

DMX

equation immediately below. (9)

(10)

Consequently to minimize the impact of the t

SYNC

it is clearly advantageous to utilize the smallest synchronization

pulse width feasible.

NOTE

When external synchronization is used, a propagation delay of approximately 50 ns to 100

ns exists between internal timing circuits and the SYNC signal’s falling edge, which may

result in reduced off-time at the highest of switching frequencies. Therefore, R

DMX

should

be adjusted downward slightly by (T

SYNC

-0.1 μs)/T

SYNC

to compensate. At lower SYNC

frequencies, this delay becomes an insignificant fraction of the PWM period, and can be

neglected.