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CRMS

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CRMS

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UCC28070

SLUS794E – NOVEMBER 2007–REVISED APRIL 2011

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APPLICATION INFORMATION

THEORY OF OPERATION

Interleaving

One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequency

ripple components of both the input current and the current into the output capacitor of the PFC pre-regulator.

Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the

burden of filtering conducted-EMI noise and helps reduce the EMI filter and C

sizes. Additionally, reduced

high-frequency ripple current into the PFC output capacitor, C

OUT

, helps to reduce its size and cost. Furthermore,

with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a

single-phase design [1].

Ripple current reduction due to interleaving is often referred to as “ripple cancellation”, but strictly speaking, the

peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other

than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual

phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator,

those of a 2-phase interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation, the

frequency of the interleaved ripple, at both the input and output, is 2 x f

PWM

On the input, 180° interleaving reduces the peak-to-peak ripple amplitude to 1/2 or less of the ripple amplitude of

the equivalent single-phase current.

On the output, 180° interleaving reduces the rms value of the PFC-generated ripple current in the output

capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50%.

This can be seen in the following derivations, adapting the method by Erickson [2].

In a single-phase PFC pre-regulator, the total rms capacitor current contributed by the PFC stage at all

duty-cycles can be shown to be approximated by:

(1)

In a dual-phase interleaved PFC pre-regulator, the total rms capacitor current contributed by the PFC stage for D

> 50% can be shown to be approximated by:

(2)

In these equations, I

= average PFC output load current, V

= average PFC output voltage, V

= peak of the

input ac-line voltage, and η = efficiency of the PFC stage at these conditions. It can be seen that the quantity

under the radical for i

Crms2φ

is slightly smaller than 1/2 of that under the radical for i

Crms1φ

. The rms currents

shown contain both the low-frequency and the high-frequency components of the PFC output current.

Interleaving reduces the high-frequency component, but not the low-frequency component.