Datasheet

UCC28070A
www.ti.com SLUSAW0 –MARCH 2012
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
RATING UNIT
Human Body Model (HBM) 2,000
V
Charged Device Model (CDM) 500
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VCC Input Voltage (from a low-impedance source) V
UVLO
+ 1 V 21 V
VREF Load Current 2 mA
VINAC Input Voltage Range 0 3
IMO Voltage Range 0 3.3 V
PKLMT, CSA, & CSB Voltage Range 0 3.6
RSYNTH Resistance (R
SYN
) 15 750
kΩ
RDM Resistance (R
RDM
) 30 330
THERMAL INFORMATION
THERMAL METRIC
(1)
UNITS
PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
θ
JB
Junction-to-board thermal resistance
(4)
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
ψ
JB
Junction-to-board characterization parameter
(6)
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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