Datasheet

UCC28063
SLUSAO7 – SEPTEMBER 2011 www.ti.com
RECOMMENDED OPERATING CONDITIONS
All voltages are with respect to GND, −40°C < T
J
= T
A
< 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
PARAMETER MIN MAX UNIT
VCC input voltage from a low-impedance source 14 21 V
VCC input current from a high-impedance source 8 18
mA
VREF load current 0 −2
VINAC input voltage 0 6 V
ZCDA, ZCDB series resistor 20 80
kΩ
TSET resistor to program PWM on-time 66.5 400
HVSEN input voltage 0.8 4.5 V
THERMAL INFORMATION
UCC28063
THERMAL METRIC
(1)
SOIC (D) UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
91.6
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
52.1
θ
JB
Junction-to-board thermal resistance
(4)
48.6 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
14.9
ψ
JB
Junction-to-board characterization parameter
(6)
48.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): UCC28063