Datasheet

S Q
QR
S Q
QR
+
+
+
EN
LOW_OV Latch
DROPOUT
VSENSE
COMP
OC
20mV
5.9V
3.0V
DIS_EA
STOP GDA
STOP GDB
DIS_High_Gain
PHASE_B_OFF
4μA 2kΩ
COMP Discharge Latch
Gain -Disable Latch
+
+
6.36V
1.25V
+
+
6.67V
6.48V
S Q
QR
HIGH_OV
LOW_OV
VCC
S Q
QR
HIGH_OV Latch
BROWNOUT
HVSEN_OV
TSET_FLT
UVLO
CS_OPEN
TSD
EN
OV-Clear
UCC28063
SLUSAO7 – SEPTEMBER 2011 www.ti.com
Fault Logic Diagram
Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states.
Figure 33. Fault Logic with VSENSE Detections and Error Amplifier Control
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Product Folder Link(s): UCC28063