Datasheet

FLSF _ OV
PWM OFF
V
V
2.5 V 4.87 V
-
=
PWM ON PWM OFF HV _ HYS HV _ UPPER
V V I R
- -
= +
PWM ON PWM OFF
HV _ UPPER
HV _ HYS
V V
R
I
- -
-
=
HV _UPPER
HV _LOWER
PWM OFF
R
R
V
1
2.5 V
-
=
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-
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UCC28063
www.ti.com SLUSAO7 –SEPTEMBER 2011
VREF
VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as
serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance
0.1-μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external
circuits should not exceed a few milli-amperes and should not be pulsing.
The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below
the Enable threshold. This output can only source current and is unable to accept current into the pin.
VCC
VCC is usually connected to a bias supply of between 13 V and 21 V. To minimize switching ripple voltage on
VCC, it should be by-passed with a low-impedance capacitor as close to the VCC and GND pins as possible.
The capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the
highest operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener
diode is recommended to prevent excessive current into VCC.
The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or
has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and
most circuits within the device are disabled and VCC current falls significantly below the normal operating level.
The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during
pre-powerup and standby conditions.
Control of Downstream Converter
In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (I
HV_HYS
) is enabled as
long as the output voltage remains below a programmed threshold. When the output voltage exceeds that
threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At
the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream
converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider
ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When
designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.
Because there are two thresholds associated with the HVSEN input detected through a single resistor divider,
the PWMCNTL turn-off voltage, V
PWM-OFF
, is linked to the FailSafe OVP voltage, V
FLSF_OV
, as shown by
Equation 14:
(14)
Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL
turn-on voltage, V
PWM-ON
, is programmed by choosing the upper divider resistor value in consideration with the
HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then
calculated as shown in Equation 17.
(15)
(16)
(17)
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