Datasheet

UCC28063
www.ti.com
SLUSAO7 SEPTEMBER 2011
PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN
> 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see
PHB pin). Otherwise, PWMCNTL is high-impedance.
Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus
COMP voltage and the minimum switching period at the gate-drive outputs. Protection circuits prevent the
controller from operating if the TSET input is in an open-circuit or short-circuit condition. As long as this pin is
open-circuited, it triggers a full soft-start condition. If this pin becomes shorted to GND, its current is limited and
also triggers a soft-start condition.
Bias Supply Input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a
0.1-μF or larger ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This bias
supply powers all circuits within the device and must be capable of delivering the steady-state dc current plus the
transient power-MOSFET gate-charging current. Input bias current is very low during undervoltage-lockout
(UVLO) or stand-by conditions (VSENSE < 1.25 V).
Input AC Voltage Sense: For normal operation, connect this pin to a voltage divider across the rectified input
power mains. When the voltage on VINAC remains below the brownout threshold for longer than the brownout
filter time, the device enters a brownout mode, both output drivers are disabled and a full soft-start is triggered.
Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the
desired brownout hysteresis based on the hysteresis current. A dropout condition is triggered when VINAC
remains below the dropout threshold for longer than the dropout filter time. The error amplifier is disabled and an
internal 4-μA current source discharges COMP for the duration of the dropout condition. The dropout condition is
immediately cleared and normal operation resumes when VINAC exceeds the dropout-clear threshold.
Voltage Reference Output: Connect a 0.1-μF or larger ceramic bypass capacitor from this pin to AGND. VREF
turns off during UVLO and VSENSE-disable to save bias current and increase stand-by efficiency. This reference
output can be used to bias other circuits requiring less than a few milliamperes of non-pulsing total supply
current.
Output DC Voltage Sense: Connect this pin to a voltage divider across the output of the power converter. In a
closed-loop system, the voltage at VSENSE is regulated to the error amplifier reference voltage. Select the
output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to analog
ground (AGND) through a separate short trace for best output regulation accuracy and noise immunity. Controller
operation may be enabled when VSENSE voltage exceeds the 1.25-V enable threshold. VSENSE can be pulled
low by an open-drain logic output, or >6-V logic output in series with a low-leakage diode, to disable the outputs
and reduce VCC current. Two levels of output overvoltage are detected at this input. If VSENSE exceeds the
first-level overvoltage protection threshold V
LOW_OV
, an internal 2-kΩ resistor is applied to COMP to quickly
reduce gate-drive on-time. If VSENSE continues to rise past the second-level threshold V
HIGH_OV
, GDA and GDB
are immediately latched off. This latch is cleared when VSENSE falls below the OV-clear threshold. If VSENSE
becomes disconnected, open-loop protection provides an internal current source to pull VSENSE low, which
disables the controller and triggers a soft-start condition.
Zero Current Detection Inputs: These inputs are used to detect a negative-going edge when the boost inductor
current in each respective phase goes to zero. The inputs are clamped between 0 V and 3 V. Connect each pin
through a current limiting resistor to the zero-crossing detection (ZCD) winding of the corresponding boost
inductor. The resistor value should be chosen to limit the clamping currents to less than ±3 mA. The inductor
winding polarity must be arranged so that this ZCD voltage falls when the inductor current decays to zero. When
the inductor current falls to zero, the ZCD input must drop below the falling threshold (approximately 1 V) to
cause the gate drive output to rise. Subsequently, when the power-MOSFET turns off, the ZCD input must rise
above the rising threshold (approximately 1.7 V) to arm the logic for another falling ZCD edge.
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