Datasheet

UCC28063
SLUSAO7 – SEPTEMBER 2011 www.ti.com
Detailed Pin Description
Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal
returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals
of the power components from interference with the low-current analog circuits.
Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance
current source. Connect voltage-regulation loop-compensation components from this pin to AGND. The on-time
seen at the gate-drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV.
During normal operation, the error amplifier maintains a transconductance of 55 μS for small-signal disturbances
on VSENSE, and shifts to ~290 μS when VSENSE deviates more than +/-5% from VSENSEreg. During an
AC-line Dropout condition, the error amplifier output is disabled and an internal 4-μA source discharges COMP
for the duration of the Dropout condition. During a VSENSE-based OV event, an internal 2-kΩ resistor is applied
from COMP to GND until the OV condition clears. During soft-start triggering events (UVLO, Disable, Brownout,
HVSEN over-voltage, TSET-Fault, CS open-circuit, or Thermal Shutdown), the error-amp output is disabled and
COMP is pulled low by an internal 2-kΩ resistor. The soft-start condition begins only after the triggering event
clears and COMP has been discharged below 20 mV, ensuring that the circuit restarts with a low COMP voltage
and a short on-time. (Do not connect COMP to a low-impedance source that would interfere with COMP falling
below 20 mV.) During Soft-Start, the error amplifier high transconductance is enabled and COMP current is -125
μA as long as VSENSE < VREF/2. Once VSENSE exceeds VREF/2, the high gain is disabled and only the
small-signal gain capability is available with a maximum COMP current of approximately -16 μA. Normal
operation resumes once VSENSE > 0.983VREF (~5.9 V).
Current Sense Input: Connect the current-sense resistor and the negative terminal of the diode bridge to this
pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current
increases, the voltage on CS will go more negative. This cycle-by-cycle over-current protection limits input
current by turning off both gate driver outputs (GDx) when CS is more negative than the CS rising threshold
(approximately -200 mV in two-phase operation and approximately -167 mV in single-phase and phase-fail
condition). The gate drive outputs will remain low until CS falls to the CS falling threshold (approx. -15 mV).
Current sense is blanked for approximately 100 ns following the rising and falling edge of either GDx output. This
filters noise that may occur from gate-drive current or when inductor current switches from a power FET to a
boost diode. In most cases, no additional current sense filtering is required. If external filtering is deemed
necessary, or to prevent excessive negative voltage on the CS pin during AC-inrush conditions, a series resistor
is recommended to connect the current sensing resistor to the CS pin. Due to the CS bias current, this external
resistor should be less than 100 Ω to maintain accuracy. If the CS pin becomes open-circuited, the voltage on
CS floats up to about +1.5 V. This condition is detected and treated as a soft-start-triggering fault condition (CS
open-circuit).
Channel A and Channel B Gate Drive Output: Connect these pins to the gate of the power FET for each
phase through the shortest connection practicable. If it is necessary to use a trace longer than 0.5 inch (12.6
mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be damped by
adding a low-value resistor in series with GDA and GDB.
High Voltage Output Sense: The UCC28063 incorporates FailSafe OVP so that any single failure does not
allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN but
their actions are different if either pin exceeds their respective over-voltage thresholds. Using two pins to monitor
for over-voltage provides redundant protection and fault tolerance. When HVSEN exceeds its over-voltage
threshold, it triggers a full soft-start of the controller. HVSEN can also be used to enable a downstream power
converter when the voltage on HVSEN is within the operating region. When HVSEN is greater than 2.5 V, the
PWMCNTL output may be driven Low (provided no other fault exists). When HVSEN falls below 2.5 V, the
PWMCNTL output becomes high-impedance. Select the HVSEN divider ratio for the desired over-voltage and
power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis based on
the hysteresis current. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts
the UCC28063 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND
is recommended to filter noise and avoid false over-voltage shutdown.
Phase-B Enable/Disable: When the voltage applied to this pin is below the Phase-B enable threshold, Phase B
of the boost converter and the Phase Fail detector are disabled. The commanded on-time for Phase A is
immediately doubled when Phase B is disabled, which helps keep COMP voltage constant during the
phase-management transient. The PHB pin allows the user to add external phase-management control circuitry,
if desired. To disable phase-management, connect the PHB pin to the VREF pin.
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