Datasheet

Recommended PCB Device Layout
CF4
UCC28061
www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, the timing setting resistor R
T
should be put as
close as possible to the TSET pin and returned to the analog ground. See Figure 29 for a recommended
component layout and placement.
Figure 29. Recommended PCB Layout
NOTE:
PHB and VREF Pins are connected by a Jumper on the back of the board.
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