Datasheet
Table Of Contents
- NATURAL INTERLEAVING FEATURES
- SYSTEM FEATURES
- APPLICATIONS
- CONTENTS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTROSTATIC DISCHARGE (ESD) PROTECTION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Theory of Operation
- On-Time Control, Maximum Frequency Limiting, and Restart Timer
- Natural Interleaving
- Phase Management
- Zero Crossing Detection and Valley Switching
- Brownout Protection
- Failsafe OVP—Output Over-Voltage Protection
- Over-Current Protection
- Phase Fail Protection
- Distortion Reduction
- Improved Error Amplifier
- Open-Loop Protection
- Soft-Start
- Light-Load Operation
- Command for the Downstream Converter
- VCC Undervoltage Protection
- VCC
- DESIGN EXAMPLE
- ADDITIONAL REFERENCES

Zero Crossing Detection and Valley Switching
R
C
ZCD
CT
R1
C
R2
ZCD
CT
Brownout Protection
Failsafe OVP — Output Over-Voltage Protection
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current crosses 0. Because of the
resonance between the boost inductor and the parasitic capacitor at the MOSFET drain node, part of the energy
stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when the
rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junction
capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay,
the MOSFET can be turned on at the valley of its resonating drain voltage (valley switching). In this way, the
energy recovery can be maximized and switching loss is minimized.
The RC time constant is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 24 .
Because the ZCD pin is internally clamped, a more accurate delay can also be realized by using Figure 25 .
Figure 24. Simple RC Delay Circuit
Figure 25. More Accurate Time Delay Circuit
As the power line RMS voltage decreases, RMS input current increases to maintain the output voltage constant
for a specific load. Brownout protection prevents the RMS input current from exceeding a safe operating level.
Power line RMS voltage is sensed at VINAC. When the voltage applied to VINAC fails to exceed the brownout
threshold for the brownout filter time, a brownout condition is detected and both gate drive outputs immediately
pull low. During brownout, COMP is actively pulled low. Gate drive outputs remain low until the voltage on VINAC
rises above the brownout threshold. After a brownout, the power stage soft-starts as COMP rises.
The brownout detection threshold and its hysteresis are set by the voltage divider ratio and resistor values.
Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on line peak
voltage. The peak VINAC voltage can be easily translated into RMS value. Suggested resistor values for the
voltage divider are 3 M Ω ± 1% from the rectified input voltage to VINAC and 46.4 k Ω ± 1% from VINAC to ground.
These resistors set the typical thresholds for RMS line voltages, as shown in Table 1 .
Table 1. Brownout Thresholds
THRESHOLD BROWNOUT (RMS)
Falling 65 V
Rising 79.8 V
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses an over-voltage condition. The output voltage can still maintain a safe level with either loop failure. The
device is re-enabled when both sense inputs fall back into the normal range. At that time, the gate drive outputs
resume switching under PWM control. Output over-voltage does not cause soft-start and the COMP pin is not
discharged during an output over-voltage event.
18 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061