Datasheet

APPLICATION INFORMATION
Theory of Operation
I (t)=
PEAK
VINAC(t) T´
ON
L
(1)
I (t)=
AVG
VINAC(t) T´
ON
2 L´
(2)
On-Time Control, Maximum Frequency Limiting, and Restart Timer
T =K (V 125mV)-
ON T COMP
(3)
T =K 4.825V´
ON(max) T
(4)
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com
The UCC28061 contains the control circuits for two boost pulse-width modulation (PWM) power converters. The
boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on
the error amplifier output. Each power converter then turns off the power MOSFET until current in the boost
inductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor
current decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave of
current, with peak current set by the on-time and power mains input voltage, as shown in Equation 1 .
The average line current is exactly equal to half of the peak line current, as shown in Equation 2 .
With T
ON
and L being essentially constant during an ac line period, the resulting triangular current waveform
during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line
voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.
The outputs of the two PWMs operate 180 ° out-of-phase so that power-line ripple current for the two PWMs is
greatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the input
and output, allowing the reduction in size and cost of input and output filters.
Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches in
inductor values do not affect the phase relationship.
Gate drive on-time varies with the error amplifier output voltage by a factor called K
T
, as shown in Equation 3 .
Where:
V
COMP
is the output of the error amplifier, and 125 mV is a modulator offset.
To provide smooth transition between two-phase and single-phase operation, K
T
increases by a factor of two in
single-phase mode:
• K
TLS
= 2 × K
TL
; active in single-phase operation
The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulator
offset, limits on-time to Equation 4 .
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage level.
The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the
minimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input
has not transitioned high-to-low for approximately 200 µ s. To prevent the circuit from operating in continuous
conduction mode (CCM), the restart time does not trigger turn-on until both phase currents return to 0.
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