Datasheet
Table Of Contents
- NATURAL INTERLEAVING FEATURES
- SYSTEM FEATURES
- APPLICATIONS
- CONTENTS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTROSTATIC DISCHARGE (ESD) PROTECTION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Theory of Operation
- On-Time Control, Maximum Frequency Limiting, and Restart Timer
- Natural Interleaving
- Phase Management
- Zero Crossing Detection and Valley Switching
- Brownout Protection
- Failsafe OVP—Output Over-Voltage Protection
- Over-Current Protection
- Phase Fail Protection
- Distortion Reduction
- Improved Error Amplifier
- Open-Loop Protection
- Soft-Start
- Light-Load Operation
- Command for the Downstream Converter
- VCC Undervoltage Protection
- VCC
- DESIGN EXAMPLE
- ADDITIONAL REFERENCES

GateDriveSinkCurrent mA-
2.5
2.0
1.5
1.0
0
0 1 2 3 4 5 6 7 8 9 10
GateDriveVoltage V-
0.5
T = 40 C- °
J
T =+25 C
J
°
T =+125 C
J
°
T Temperature C°
J
- -
15
14
13
5
-40 -20 0 20 40 60 100 120
GateDriveVoltage V-
12
11
10
9
8
7
6
ClampedVCC 15V³
UnclampedVCC=12V
R =2kW
LOAD
60
R TimeSettingResistor kW
TSET
- -
10
9
8
7
6
0
60 80 100 180 200 220 240 260 280
K On-TimeFactor
s/V
- m
T
-
5
4
3
2
1
120 140 160
K
TL
T Temperature C°
J
- -
9
8
7
0
-40 -20 0 20 40 60 80 100 120
K On-TimeFactor s/V-
m
TL
-
6
5
4
3
2
1
R =266kW
TSET
R =133kW
TSET
R =66kW
TSET
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω ; all voltages
are with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
GATE DRIVE OUTPUT IN UVLO GATE DRIVE HIGH VOLTAGE
vs vs
SINK CURRENT TEMPERATURE
Figure 17. Figure 18.
ON-TIME FACTOR ON-TIME FACTOR PHASE A AND B
vs vs
TIME SETTING RESISTOR TEMPERATURE
Figure 19. Figure 20.
14 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061