Datasheet

ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
UCC28060
www.ti.com .................................................................................................................................................... SLUS767E – MAY 2007 – REVISED NOVEMBER 2008
All voltages are with respect to GND, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
UCC28060 UNIT
VCC
(2)
– 0.5 to +21
PWMCNTL – 0.5 to +20
Input voltage range V
COMP
(3)
, CS, PHB, HVSEN
(4)
, VINAC
(4)
, VSENSE
(4)
– 0.5 to +7
ZCDA, ZCDB – 0.5 to +4
Continuous input current VCC 20
Input current PWMCNTL 10
Input current range ZCDA, ZCDB, VSENSE – 5 to +5 mA
Output current VREF – 10
Continuous gate current GDA, GDB
(5)
± 25
Operating – 40 to +125
Junction temperature, T
J
Storage – 65 to +150 ° C
Lead temperature, T
SOL
Soldering, 10s +260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
(2) Voltage on VCC is internally clamped. VCC may exceed the absolute maximum input voltage if the source is current limited below the
absolute maximum continuous VCC input current level.
(3) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
(4) In normal use, VINAC, VSENSE, and HVSEN are connected to resistors and are internally limited in voltage swing. Although not
recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as ± 10 mA from high voltage
sources.
(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp ringing due to stray inductance. See Figure 13 and Figure 14 for details.
THERMAL IMPEDANCE
PACKAGE JUNCTION-TO-AMBIENT T
A
= +25 ° C POWER RATING T
A
= +85 ° C POWER RATING
SOIC 16-Pin (D) 140 ° C/W
(1)
890 mW
(1)
460 mW
(1)
(1) Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal
resistance. This number is only a general guide; see TI document SPRA953 device Thermal Metrics.
All voltages are with respect to GND, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
MIN MAX UNIT
VCC input voltage from a low-impedance source 14 21 V
VCC input current from a high-impedance source 8 18 mA
VREF load current 0 – 2 mA
VINAC Input voltage 0 6 V
ZCDA, ZCDB series resistor 20 80 k Ω
TSET resistor to program PWM on-time 66.5 270 k Ω
HVSEN input voltage 0.8 4.5 V
PWMCNTL pull-up resistor to VREF 1 10 k Ω
RATING UNIT
Human body model (HBM) 2000 V
Charged device model (CDM) 500 V
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