Datasheet

Converter Timing
f =
MIN
=39.2kHz
P L1
OUT MAX
´
=
h (V )´
IN_MIN
2
V Ö
IN_MIN
´ 2
V
OUT
1 -
300W 390 Hm´
0.92 (85V)´
2
85V Ö´ 2
390V
1 -
(36)
R =
TSET
» W121k
4.85V 4 s fm´ ´
MIN
=
133kW
V Ö
IN_MIN
´
2
V
OUT
1 -
4.85V 4 s 39.2kHzm´ ´
133kW
85V Ö´
2
390V
1 -
(37)
f =
MAX
» 550kHz
2 s Rm ´
T
=
133kW
2 s 121km W´
133kW
(38)
Programming V
OUT
R =3MW
C
(39)
V =6V
REF
(40)
R =
D
» W47k
(V V )-
OUT REF
=
V R
REF C
´
(390V 6V)-
6V 3M´ W
(41)
V =6.45V
OVP
=418V
R
D
=6.45V
R +R
C D
47kW
3M +47kW W
(42)
Loop Compensation
g =96 Sm
m
(43)
H= » 0.015=
V
REF
V
OUT
6V
390V
(44)
R =
Z
=6.313k 6.34k» WW=
100mV
V H g
RIPPLE m
´ ´
100mV
11V 0.015 96 Sm´ ´
(45)
UCC28060
www.ti.com .................................................................................................................................................... SLUS767E – MAY 2007 – REVISED NOVEMBER 2008
Select the timing resistor, R
TSET
, for the correct on-time (T
ON
) based on K
TL
, as shown in Equation 36 . To ensure
proper operation, the timing must be set based on the highest boost inductance (L1
MAX
). In this design example,
the boost inductor could be as high as 390 µ H, based on line and load conditions, as shown in Equation 37 .
This result sets the maximum frequency clamp (f
MAX
), as shown in Equation 38 , which improves efficiency at light
load.
Resistor R
C
is selected to minimize error because of VSENSE input bias current and minimize loading on the
power line when the PFC is disabled. Construct resistor R
C
from two or more resistors in series to meet
high-voltage requirements. R
C
was also selected to be of a similar value of R
A
and R
E
to simplify the bill of
materials and reduce design costs.
Based on the resistor values shown in Equation 39 to Equation 41 , the primary output over-voltage protection
threshold should be as shown in Equation 42 :
Resistor R
Z
is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low input current harmonic distortion.
The transconductance amplifier gain is shown in Equation 43 :
The voltage divider feedback gain is shown in Equation 44 and Equation 45 :
C
Z
is then set to add 45 ° of phase margin at 1/5th of the switching frequency, as shown in Equation 46 :
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