Datasheet

UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
8
www.ti.com
BLOCK DESCRIPTION
UVLO and Reference Block
This block generates a precision reference voltage used to obtain tightly controlled UVLO threshold. In addition
to generating a 2.5-V reference for the non-inverting terminal of the g
M
amplifier, it generates the reference
voltages for blocks such as OVP, enable, zero power and multiplier. An internal rail of 7.5 V is also generated
to drive all the internal blocks.
Error Amplifier
The voltage error amplifier in UCC3805x is a transcoductance amplifier with a typical transconductance value
of 90 μS. The advantage in using a transconductance amplifier is that the inverting input of the amplifier is solely
determined by the external resistive-divider from the output voltage and not the transient behavior of the
amplifier itself. This allows the VO_SNS pin to be used for sensing over voltage conditions.
The sink and source capability of the error amplifier is approximately 10 μA during normal operation of the
amplifier. But when the VO_SNS pin voltage is beyond the normal operating conditions (VO_SNS >1.05 × V
REF
,
VO_SNS < 0.88 × V
REF
), additional circuitry to enhance the slew-rate of the amplifier is activated. Enhanced
slew-rate of the compensation capacitor results in a faster start-up and transient response. This prevents the
output voltage from drifting too high or too low, which can happen if the compensation capacitor were to be
slewed by the normal slewing current of 10-μA. When VO_SNS rises above the normal range, the enhanced
sink current capability is in excess of 1 mA. When VO_SNS falls below the normal range, the UCC38050 can
source more than 1 mA and the UCC38051 sources approximately 300 μA. The limited source current in the
UCC38051 helps to gradually increase the error voltage on the COMP pin preventing a step increase in line
current. The actual rate of increase of V
COMP
depends on the compensation network connected to the COMP
pin.
Zero Current Detection and Re-Start Timer Blocks
When the boost inductor current becomes zero, the voltage at the power MOSFET drain end falls. This is
indirectly sensed with a secondary winding that is connected to the ZCD pin. The internal active clamp circuitry
prevents the voltage from going to a negative or a high positive value. The clamp has the sink and source
capability of 10 mA. The resistor value in series with the secondary winding should be chosen to limit the ZCD
current to less than 10 mA. The rising edge threshold of the ZCD comparator can be as high as 2.0 V. The
auxiliary winding should be chosen such that the positive voltage (when the power MOSFET is off) at the ZCD
pin is in excess of 2.0 V.
The restart timer attempts to set the gate drive high in case the gate drive remains off for more than 400 μs
nominally. The minimum guaranteed time period of the timer is 200 μs. This translates to a minimum switching
frequency of 5 kHz. In other words, the boost inductor value should be chosen for switching frequencies greater
than 5 kHz.
Enable Block
The gate drive signal is held low if the voltage at the VO_SNS pin is less than the ENABLE threshold. This feature
can be used to disable the converter by pulling VO_SNS low. If the output feedback path is broken, VO_SNS
is pulled to ground and the output is disabled to protect the power stage.