Datasheet

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Output Voltage Set Point
1
2
REF FB
FB
OUT REF
V R
R
V V
=
-
2
5 1
13 04
390 5
FB
V M
R . k
V V
´ W
= = W
-
1 2
2
FB FB
OUT ( OVP ) OVP
FB
R R
V VSENSE
R
æ ö
+
=
ç ÷
è ø
1 13
5 25 410 7
13
OUT ( OVP )
M k
V . V . V
k
W + W
æ ö
= ´ =
ç ÷
W
è ø
1 2
2
FB FB
OUT ( UVD ) UVD
FB
R R
V VSENSE
R
æ ö
+
=
ç ÷
è ø
1 13
4 75 371 6
13
OUT ( UVD )
M k
V . V . V
k
W + W
æ ö
= ´ =
ç ÷
W
è ø
UCC28019
SLUS755B – APRIL 2007 – REVISED DECEMBER 2007
For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 M Ω
for the top voltage feedback divider resistor, R
FB1
. Multiple resistors in series are used due to the maximum
allowable voltage across each. Using the internal 5-V reference, V
REF
, select the bottom divider resistor, R
FB2
, to
meet the output voltage design goals.
Using 13 k Ω for R
FB2
results in a nominal output voltage set point of 391 V.
The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:
The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal
set-point:
A small capacitor on VSENSE must be added to filter out noise that would trigger the enhanced dynamic
response in a no-load high-line configuration. Limit the value of the filter capacitor such that the RC time constant
is less than 0.1 ms so as not to significantly reduce the control response time to output voltage deviations.
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