Datasheet

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Current Loop
ISENSE and ICOMP Functions
Pulse Width Modulator
Control Logic
Voltage Loop
Output Sensing
UCC28019
SLUS755B – APRIL 2007 – REVISED DECEMBER 2007
The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator
(PWM) stage, the external boost inductor stage, and the external current sensing resistor.
The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The
internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The
voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the
ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is
determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-line
voltage range. ICOMP is connected to 4 V internally whenever the device is in a Fault or Standby condition.
The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output
signal which is high whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined by
a non-linear function of the internal VCOMP voltage.
The PWM output signal always starts low at the beginning of the cycle, triggered by the internal clock. The output
stays low for a minimum off-time, t
OFF(min)
, after which the ramp rises linearly to intersect the ICOMP voltage. The
ramp-I
COMP
intersection determines t
OFF
, and hence D
OFF
. Since D
OFF
= V
IN
/V
OUT
by the boost-topology equation,
and since V
IN
is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor current, it follows that
the control loop forces the inductor current to follow the input voltage wave-shape to maintain boost regulation.
Therefore, the average input current is also sinusoidal in wave-shape.
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various
protection functions incorporated into the IC. The GATE output duty-cycle may be as high as 99%, but will
always have a minimum off-time t
OFF(min)
. Normal duty-cycle operation can be interrupted directly by OVP and
PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and
further inhibit output until the SS operation can begin.
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing
stage, the voltage error amplifier stage, and the non-linear gain generation.
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control
loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference
voltage.
Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable
resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves
to filter the signal in a high-noise environment. This filter time constant should generally be less than 100 µ s.
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