Datasheet

www.ti.com
+
OLP/STANDBY
0.82V
OLP/STANDBY
+
OVERVOLTAGE
5.25V
OVP
Input Brown-Out Protection
(IBOP)
+
+
VIN
ENABLE_th
1.5V
S Q
QR
VIN
BROWNOUT_th
0.82V
5V
20k
IBOP
+
V
PCL
1.08V
Soft Over Current (SOC)
V
SOC
0.73V
Peak Current Limit (PCL)
SOC
40k 40k
+
PCL
-1x
300ns
Leading Edge
Blanking
UVLO
+
+
VCC
ON
10.5V
SQ
Q R
VCC
OFF
9.5V
UVLO
R
SENSE
C
OUT
L
BST
R
ISENSEfilter
+–
Bridge
Rectifier
C
ISENSEfilter
LINE
INPUT
D
BST
V
OUT
C
CV2
R
CV
C
CV1
+
gmv
Voltage Error
Amplifier
+
gmi
C
ICOMP
S Q
QR
PWM
Comparator
K
PC
(s)
SOC
M
2
M
1
EMI Filter
ICOMP
VCOMP
C
IN
5V
65kHz
Oscillator
R
LOAD
C
VCC
Auxilary
Supply
Current
Amplifier
3
ISENSE
2
ICOMP
VINS
4
5
VCOMP
6
VSENSE
7
1
VCC
GND
8
GATE
GAIN
M
1
, K
1
EDR
+
UNDERVOLTAGE
4.75V
EDR
C
VINS
R
VINS1
R
VINS2
VCC
Gate Driver
UVLO
IBOP
OLP
S Q
QR
OVP
Pre-Drive and
Clamp Circuit
R
FB1
R
FB2
Q
BST
10k
R
GATE
C
VSENSE
+
PWM
RAMP
M
2
Min Off Time
+
SS
EDR
Fault
Logic
Fault
100µA
4V
FAULT
PCL
Clock
FAULT
4V
UCC28019
SLUS755B – APRIL 2007 – REVISED DECEMBER 2007
Figure 18. Block Diagram
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): UCC28019