Datasheet
DEVICE INFORMATION
GND
ICOMP
ISENSE
GATE
VCC
VSENSE
VCOMP
VINS
1
2
3
4
8
7
6
5
UCC28019A
www.ti.com
.................................................................................................................................................. SLUS828B – DECEMBER 2008 – REVISED APRIL 2009
SOIC PDIP Top View
TERMINAL FUNCTIONS
NAME PIN # I/O FUNCTION
Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A
GATE 8 O
sink and 1.5-A source capability. Output voltage is typically clamped at 12.5 V.
GND 1 Ground: device ground reference.
Current loop compensation: Transconductance current amplifier output. A capacitor connected to
ICOMP 2 O GND provides compensation and averaging of the current sense signal in the current control loop.
The controller is disabled if the voltage on ICOMP is less than 0.6 V.
Inductor current sense: Input for the voltage across the external current sense resistor, which
represents the instantaneous current through the PFC boost inductor. This voltage is averaged by the
current amplifier to eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the
ISENSE 3 I average inductor current. Cycle-by-cycle Peak Current Limit (PCL) immediately shuts off the GATE
drive if the peak-limit voltage is exceeded. An internal 1.5- µ A current source pulls ISENSE above 0.1
V to shut down PFC operation if this pin becomes open-circuited. Use a 220- Ω resistor between this
pin and the current sense resistor to limit inrush-surge currents into this pin.
Device supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until
VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off
VCC 7
(UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µ F minimum value must be connected
from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage.
Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor
network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC,
VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP
VCOMP 5 O is charged until the VSENSE voltage reaches 99% of its nominal regulation level. When Enhanced
Dynamic Response (EDR) is engaged, a higher transconductance is applied to VCOMP to reduce the
charge time for faster transient response. Soft Start is programmed by the capacitance on this pin.
The EDR higher transconductance is inhibited during Soft Start.
Input ac voltage sense: A filtered resistor-divider network connects from this pin to the rectified-mains
node. Input Brown-Out Protection (IBOP) detects when the system ac-input voltage is above a
user-defined normal operating level, or below a user-defined “ brown-out ” level. At startup the
VINS 4 I controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft start. The
controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not
resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft
start.
Output voltage sense: An external resistor-divider network connected from this pin to the PFC output
voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small
capacitor from this pin to GND filters high-frequency noise. Standby mode disables the controller and
discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8 V. An
VSENSE 6 I internal 100-nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin
disconnection. Output Over-Voltage Protection (OVP) disables the GATE output when VSENSE
exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the
output voltage to its normal regulation level when a system line or load step causes VSENSE to fall
below 95% of the reference voltage.
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