Datasheet

Control Logic
Voltage Loop
Output Sensing
Voltage Error Amplifier
UCC28019A
www.ti.com .................................................................................................................................................. SLUS828B – DECEMBER 2008 – REVISED APRIL 2009
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various
protection functions incorporated into the device. The GATE output duty-cycle may be as high as 99%, but will
always have a minimum off-time t
OFF_min
. Normal duty-cycle operation can be interrupted directly by OVP and
PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and
further inhibit output until the SS operation can begin.
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing
stage, the voltage error amplifier stage, and the non-linear gain generation.
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control
loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference
voltage.
Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable
resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves
to filter the signal in a high-noise environment. This filter time constant should generally be less than 100 µ s.
The transconductance error amplifier (g
mv
) generates an output current proportional to the difference between the
voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges
the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system
operating conditions. Proper selection of the compensation network components leads to a stable PFC
pre-regulator over the entire ac-line range and 0-100% load range. The total capacitance also determines the
rate-of-rise of the VCOMP voltage at soft start, as discussed earlier.
The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge the
compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays
complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias
voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large
capacitor could be left with substantial voltage on it, negating the benefit of a subsequent soft start. The
UCC28019A incorporates a parallel discharge path which operates without VCC bias, to further discharge the
compensation network after VCC is removed.
When output voltage perturbations greater than 5% appear at the VSENSE input, the amplifier moves out of
linear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSE
returns within 5% of regulation. On an under-voltage, the UVD function invokes EDR which immediately
increases the voltage error amplifier transconductance to about 440 µ S. This higher gain facilitates faster
charging of the compensation capacitors to the new operating level.
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