Datasheet
Current Sense Resistor, R
ISENSE
1 1
SOC(min)
ISENSE
L _ PEAK (max)
V
R
. I
£
(5)
2
RISENSE IN _ RMS (max) ISENSE
P ( I ) R=
(6)
PCL
PCL
ISENSE
V
I
R
=
(7)
Gate Driver
VCC
VCC
GATE
C
OUT
L
BOOST
D
BOOST
V
OUT
Rectified
AC
GND
Gate Driver
R
GATE
UVLO
IBOP
OLP
From
PWM
Latch
10k
S Q
QR
PCL
OVP
CLOCK
Pre-Drive and
Clamp Circuit
Q
BOOST
Fault
Logic
FAULT
UCC28019A
www.ti.com
.................................................................................................................................................. SLUS828B – DECEMBER 2008 – REVISED APRIL 2009
The current sense resistor, R
ISENSE
, is sized using the minimum threshold value of Soft Over Current (SOC),
V
SOC(min)
= 0.66 V. To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle,
the resistor is sized for an overload current of 10% more than the peak inductor current,
Since R
ISENSE
sees the average input current, worst-case power dissipation occurs at input low-line when input
current is at its maximum. Power dissipated by the sense resistor is given by:
Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor
reaches the PCL threshold, V
PCL
. The absolute maximum peak current, I
PCL
, is given by:
The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET
gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to
12.5 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the Off state. An
external gate drive resistor, R
GATE
, can be used to limit the rise and fall times and dampen ringing caused by
parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of the resistor
depends upon the parasitic elements associated with the layout and other considerations. A 10-k Ω resistor close
to the gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and helps protect
against inadvertent dv/dt-triggered turn-on.
Figure 25. Gate Driver
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