Datasheet

UCC27611

SLUSBA5B –DECEMBER 2012

www.ti.com

PCB Layout Recommendation

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device

operation and design robustness. The UCC27611 gate driver incorporates short-propagation delays and powerful

output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power

switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current capability is even

higher (4-A and 6-A peak current is at VDD = 12 V). Very high di and dt can cause unacceptable ringing if the

trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly

recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to power device in order to minimize the length of high-current

traces between the output pins and the gate of the power device.

• Locate the VDD and VREF bypass capacitors between VDD, VREF and GND as close as possible to the

driver with minimal trace length to improve the noise filtering. These capacitors support high-peak current

being drawn from VDD during turn on of power MOSFET. The use of low inductance SMD components such

as chip resistors and chip capacitors is highly recommended.

• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD, VREF bypass

capacitors) should be minimized as much as possible in order to keep the stray inductance to a minimum.

High dI and dt is established in these loops at two instances – during turn-on and turn-off transients, which

will induce significant voltage transients on the output pin of the driver device and gate of the power switch.

• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.

• Separate power traces and signal traces, such as output and input signals.

• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of

the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM

controller etc at one, single point. The connected paths should be as short as possible to reduce inductance

and be as wide as possible to reduce resistance.

• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals

during transition. The ground plane must not be a conduction path for any current loop. Instead the ground

plane must be connected to the star-point with one single trace to establish the ground potential. In addition

to noise shielding, the ground plane can help in power dissipation as well.

• In noisy environments, it may be necessary to tie the unused Input pin of UCC27611 to VDD or VREF (in

case of IN+) or GND (in case of IN-) using short traces in order to ensure that the output is enabled and to

prevent noise from causing malfunction in the output.

Figure 22. PCB Layout Recommendation

Product Folder Links: UCC27611