Datasheet

UCC27611
SLUSBA5B –DECEMBER 2012 www.ti.com
Operating Supply Current
The UCC27611 feature very low quiescent I
DD
current. The total supply current is the sum of the quiescent IDD
current, the average I
OUT
current due to switching and finally any current related to pull-up resistors on the
unused input pin. For example when the inverting input pin is pulled low additional current is drawn from VDD
supply through the pull-up resistors (refer to DEVICE INFORMATION for the device Block Diagram). Knowing
the operating frequency (f
SW
) and the MOSFET gate (Q
G
) charge at the drive voltage being used, the average
I
OUT
current can be calculated as product of Q
G
and f
SW
.
Input Stage
The input pins of the UCC27611 is based on a TTL and CMOS compatible input threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 1.95 V and typical low threshold = 1.3 V,
the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V digital
power controllers. Wider hysteresis (typ 1 V) offers enhanced noise immunity compared to traditional TTL logic
implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control of the
input pin threshold voltage levels which eases system design considerations and ensures stable operation across
temperature. The very low input capacitance on these pins reduces loading and increases switching speed.
The device features an important safety function wherein, whenever any of the input pins are in a floating
condition, the output of the respective channel is held in the low state. This is achieved using VDD pull-up
resistors on all the inverting inputs (IN- pin) or GND pull-down resistors on all the non-inverting input pins (IN+
pin), (refer to DEVICE INFORMATION for the device Block Diagram).
The device also features a dual input configuration with two input pins available to control the state of the output.
The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin
(IN-). The state of the output pin is dependent on the bias on both the IN+ and IN- pins. Refer to INPUT AND
OUTPUT LOGIC TRUTH TABLE input and output logic truth table and the Typical Application Diagram, for
additional clarification.
Once an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly
biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating
condition because whenever any input pin is left in a floating condition the output is disabled for safety purposes.
Alternatively, the unused input pin can effectively be used to implement an enable and disable function, as
explained below.
• In order to drive the device in a non-inverting configuration, apply the PWM control input signal to IN+ pin. In
this case, the unused input pin, IN-, must be biased low (tied to GND) in order to enable the output.
– Alternately, the IN- pin can be used to implement the enable and disable function using an external logic
signal. OUT is disabled when IN- is biased high and OUT is enabled when IN- is biased low.
• In order to drive the device in an inverting configuration, apply the PWM control input signal to IN- pin. In this
case, the unused input pin, IN+, must be biased high (eg. tied to VDD) in order to enable the output.
– Alternately, the IN+ pin can be used to implement the enable and disable function using an external logic
signal. OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
• Finally, it is worth noting that the output pin can be driven into a high state ONLY when IN+ pin is biased high
and IN- input is biased low.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a mechanical socket or PCB layout is not optimal:
• High dI and dt current from the driver output coupled with board layout parasitic can cause ground bounce.
Since the device features just one GND pin which may be referenced to the power ground, this may modify
the differential voltage between input pins and GND and trigger an unintended change of output state.
Because of fast 13-ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage.
• 1-V input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
• In the worst case, when a slow input signal is used and PCB layout is not optimal, it may be necessary to add
a small capacitor (1 nF) between input pin and ground very close to the driver device. This helps to convert
the differential mode noise with respect to the input logic circuitry into common mode noise and avoid
unintended change of output state.
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