Datasheet

UCC27611
SLUSBA5B –DECEMBER 2012 www.ti.com
APPLICATION INFORMATION
Introduction
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers and the gates of the power semiconductor devices. Further,
gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive
the gates of the switching devices. With advent of digital power, this situation will be often encountered since the
PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively turning on a
power switch. A level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V)
in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based
on NPN and PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove
inadequate with digital power since they lack level-shifting capability. Gate drivers effectively combine both the
level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-
frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-
drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in
controllers by moving gate charge power losses into itself. Finally, emerging wide band-gap power device
technologies such as GaN based switches, which are capable of supporting very high switching frequency
operation, are driving very special requirements in terms of gate drive capability. These requirements include
operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance
packages with good thermal capability. In summary gate-driver devices are extremely important components in
switching power combining benefits of high-performance, low cost, component count and board space reduction
and simplified system design.
VDD and Undervoltage Lockout
The UCC27611 devices have internal Under Voltage LockOut (UVLO) protection feature on the VDD pin supply
circuit blocks. Whenever the driver is in UVLO condition (i.e. when VDD voltage less than VON during power up
and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of
the status of the inputs. The UVLO is typically 3.8 V with 250-mV typical hysteresis. This hysteresis helps
prevent chatter when low VDD supply voltages have noise from the power supply and also when there are
droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD.
The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN wide bandgap power semiconductor devices.
For example, at power up, the UCC27611 driver output remains LOW until the VDD voltage reaches the UVLO
threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the non-
inverting operation (PWM signal applied to IN+ pin) shown below, the output remains LOW until the UVLO
threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal
applied to IN- pin) shown below the output remains LOW until the UVLO threshold is reached, and then the
output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the
output. It is worth noting that in these devices the output turns to high state only if IN+ pin is high and IN- pin is
low after the UVLO threshold is reached.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR
should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by
the load. The parallel combination of capacitors should present a low impedance characteristic for the expected
current levels and switching frequencies in the application.
10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: UCC27611