Datasheet

UCC27531

UCC27533, UCC27536

UCC27537, UCC27538

www.ti.com

SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013

Thermal Information

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal

characteristics of the package. In order for a gate driver to be useful over a particular temperature range the

package must allow for the efficient removal of the heat produced while keeping the junction temperature within

rated limits. The thermal metrics for the driver package is summarized in the ‘Thermal Information’ section of the

datasheet. For detailed information regarding the thermal information table, please refer to Application Note from

Texas Instruments entitled “IC Package Thermal Metrics” (SPRA953A).

PCB Layout

Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device

operation and design robustness. The UCC2753x gate driver incorporates short propagation delays and powerful

output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power

switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even

higher (2.5-A and 5-A peak current is at VDD = 18 V). Very high di/dt can cause unacceptable ringing if the trace

lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended

when designing with these high-speed drivers.

• Locate the driver device as close as possible to power device in order to minimize the length of high-current

traces between the driver Output pins and the gate of the power switch device.

• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal

trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD

during turn-on of power switch. The use of low inductance SMD components such as chip resistors and chip

capacitors is highly recommended.

• The turn-on and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be

minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established

in these loops at two instances – during turn-on and turn-off transients, which induces significant voltage

transients on the output pins of the driver device and gate of the power switch.

• Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux

cancellation

• Separate power traces and signal traces, such as output and input signals.

• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of

the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM

controller etc at one, single point. The connected paths should be as short as possible to reduce inductance

and be as wide as possible to reduce resistance.

• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals

during transition. The ground plane must not be a conduction path for any current loop. Instead the ground

plane must be connected to the star-point with one single trace to establish the ground potential. In addition

to noise shielding, the ground plane can help in power dissipation as well.

Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538