Datasheet

OUT
IN
VDD
VDD Threshold
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013 www.ti.com
Table 2. UCC2753x Features and Benefits
FEATURE BENEFIT
High source and sink current capability, 2.5 A and High current capability offers flexibility in employing UCC2753x device to drive a
5 A (asymmetrical). variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay. Extremely low pulse transmission distortion.
Wide VDD operating range of 10 V to 32 V. Flexibility in system design.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection. Outputs are held Low in UVLO condition, which ensures predictable, glitch-free
operation at power-up and power-down.
High UVLO of 8.9V typical ensures that power switch is not on in high-impedance
state which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in floating Safety feature, especially useful in passing abnormal condition tests during safety
condition. certification
Split output structure option (OUTH, OUTL). Allows independent optimization of turn-on and turn-off speeds using series gate
resistors.
Strong sink current (5 A) and low pull-down High immunity to high dV/dt Miller turn-on events.
impedance (0.65 Ω).
CMOS and TTL compatible input threshold logic Enhanced noise immunity, while retaining compatibility with microcontroller logic level
with wide hysteresis. input signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding -6.5 V. Enhanced signal reliability in noisy environments that experience ground bounce on
the gate driver.
VDD Under Voltage Lockout
The UCC2753x device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of
the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than
V
ON
during power-up and when VDD voltage is less than V
OFF
during power down), this circuit holds all outputs
LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops in the VDD bias voltage when the system commences switching and there is a sudden
increase in I
DD
. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si
MOSFETs, IGBTs, and emerging SiC FETs.
Figure 41. Power Up
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