Datasheet

10%
90%
Enable
Output
Low
High
Low
High
Input
t
D1
t
D2
UDG-11219
10%
90%
Enable
Output
Low
High
Low
High
Input
t
D1
t
D2
UDG-11220
10%
90%
Enable
Output
Low
High
Low
High
Input
t
D3
t
D4
UDG-11217
10%
90%
Enable
Output
Low
High
Low
High
Input
t
D3
t
D4
UDG-11218
UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 12 V, T
A
= T
J
= -40°C to 140°C, 1-µF capacitor from V
DD
to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
t
R
Rise time
(3)
C
LOAD
= 1.8 nF 7 18
t
F
Fall time
(3)
C
LOAD
= 1.8 nF 6 10
Delay matching between 2 INA = INB, OUTA and OUTB at 50% transition
t
M
1 4
channels point
Minimum input pulse width
ns
t
PW
15 25
that changes the output state
Input to output propagation
t
D1
, t
D2
C
LOAD
= 1.8 nF, 5-V input pulse 6 13 23
delay
(3)
EN to output propagation
t
D3
, t
D4
C
LOAD
= 1.8 nF, 5-V enable pulse 6 13 23
delay
(3)
(3) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4
Timing Diagrams
Figure 1. Enable Function Figure 2. Enable Function
(For Non-Inverting Input Driver Operation) (For Inverting Input Driver Operation)
Figure 3. Non-Inverting Input Driver Operation Figure 4. Inverting Input Driver Operation
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Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526