Datasheet

UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013 www.ti.com
THERMAL INFORMATION
UCC27523, UCC27523,
UCC27524, UCC27524,
UCC27525 UCC27525
THERMAL METRIC UNITS
SOIC (D) MSOP (DGN)
(1)
8 PINS 8 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
130.9 71.8
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
80.0 65.6
θ
JB
Junction-to-board thermal resistance
(4)
71.4 7.4
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
21.9 7.4
ψ
JB
Junction-to-board characterization parameter
(6)
70.9 31.5
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
n/a 19.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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THERMAL INFORMATION
UCC27524 UCC27523,
UCC27524,
UCC27525,
THERMAL METRIC UNITS
UCC27526
PDIP (P) WSON (DSD)
(1)
8 PINS 8 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
62.1 46.7
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
52.7 46.7
θ
JB
Junction-to-board thermal resistance
(4)
39.1 22.4
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
31.0 0.7
ψ
JB
Junction-to-board characterization parameter
(6)
39.1 22.6
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
n/a 9.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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