Datasheet

UCC27518

UCC27519

SLUSB33 –MAY 2012

www.ti.com

Low Propagation Delays

The UCC27518 and UCC27519 driver device features best-in-class input-to-output propagation delay of 17 ns

(typ) at VDD = 12 V. This promises the lowest level of pulse transmission distortion available from industry

standard gate driver devices for high-frequency switching applications. As seen in Figure 14, there is very little

variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns

propagation delays across the entire range of application conditions.

Thermal Information

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal

characteristics of the package. In order for a gate driver to be useful over a particular temperature range the

package must allow for the efficient removal of the heat produced while keeping the junction temperature within

rated limits. The thermal metrics for the driver package is summarized in the Thermal Information section of the

datasheet. For detailed information regarding the thermal information table, please refer to the Application Note

from Texas Instruments entitled IC Package Thermal Metrics (Texas Instruments Literature Number SPRA953A).

PCB Layout

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device

operation and design robustness. The UCC27518 and UCC27519 gate driver incorporates short-propagation

delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at

the gate of power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current

capability is even higher (4-A/4-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing

if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly

recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to power device in order to minimize the length of high-current

traces between the output pins and the gate of the power device.

• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal

trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD

during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and

chip capacitors is highly recommended.

• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) should

be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is

established in these loops at two instances – during turn-on and turn-off transients, which will induce

significant voltage transients on the output pin of the driver device and gate of the power switch.

• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.

• Separate power traces and signal traces, such as output and input signals.

• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of

the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM

controller etc at one, single point. The connected paths should be as short as possible to reduce inductance

and be as wide as possible to reduce resistance.

• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals

during transition. The ground plane must not be a conduction path for any current loop. Instead the ground

plane must be connected to the star-point with one single trace to establish the ground potential. In addition

to noise shielding, the ground plane can help in power dissipation as well.

Product Folder Link(s): UCC27518 UCC27519