Datasheet

VDD ThresholdVDD
IN+
OUT
IN -
VDD ThresholdVDD
IN+
OUT
IN -
VDD Threshold
IN-
OUT
IN+
VDD Threshold
IN-
OUT
IN+
1
2
3
5
4
EN
GND
IN+/IN-
VDD
OUT
UCC27518/19
Q1
IN
4.5 V to 18 V
C1
R1
EN V+
UCC27518
UCC27519
SLUSB33 –MAY 2012 www.ti.com
Typical Application Diagram
Typical application diagram of UCC27518 and UCC27519 devices is shown below.
Figure 18. Typical Application Diagram
VDD and Undervoltage Lockout
The UCC2751x devices have internal Under Voltage LockOut (UVLO) protection feature on the VDD pin supply
circuit blocks. Whenever the driver is in UVLO condition (i.e. when V
DD
voltage less than V
ON
during power up
and when V
DD
voltage is less than V
OFF
during power down), this circuit holds all outputs LOW, regardless of the
status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent
chatter when low V
DD
supply voltages have noise from the power supply and also when there are droops in the
VDD bias voltage when the system commences switching and there is a sudden increase in I
DD
. The capability to
operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially
suited for driving emerging GaN wide bandgap power semiconductor devices.
For example, at power up, the UCC2751x driver output remains LOW until the V
DD
voltage reaches the UVLO
threshold. The magnitude of the OUT signal rises with V
DD
until steady-state V
DD
is reached. In the non-inverting
device (PWM signal applied to IN+ pin) shown below, the output remains LOW until the UVLO threshold is
reached, and then the output is in-phase with the input. In the inverting device (PWM signal applied to IN- pin)
shown below the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with
the input.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR
should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by
the load. The parallel combination of capacitors should present a low impedance characteristic for the expected
current levels and switching frequencies in the application.
Figure 19. Power-Up (non-inverting drive) Figure 20. Power-Up (inverting drive)
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Product Folder Link(s): UCC27518 UCC27519