Datasheet

1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
Q1
IN+
4.5 V to 18 V
Non-Inverting Input
1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
Inverting Input
V+
C1
R1
VIN-
Q1
R1
4.5 V to 18 V
V+
C1
UCC27517
UCC27516
SLUSAY4C – MARCH 2012–REVISED MAY 2013 www.ti.com
TYPICAL APPLICATION DIAGRAMS
DESCRIPTION (CONTINUED)
UCC27516 and UCC27517 features a dual input design which offers flexibility of implementing both inverting (IN-
pin) and non-inverting (IN+ pin) configurations with the same device. Either the IN+ or IN- pin can be used to
control the state of the driver output. The unused input pin can be used for enable and disable function. For
safety purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when
input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to
ensure that driver output is in enabled for normal operation.
The input pin threshold of the UCC27516 and UCC27517 devices are based on TTL and CMOS compatible low-
voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and
low thresholds offers excellent noise immunity.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)(2)
OPERATING
PEAK CURRENT INPUT THRESHOLD
PART NUMBER PACKAGE TEMPERATURE RANGE,
(SOURCE/SINK) LOGIC
T
A
CMOS/TTL-Compatible
4-A/4-A
UCC27516DRS WSON 6 pin (low voltage, independent -40°C to 140°C
(Symmetrical Drive)
of VDD bias voltage)
CMOS/TTL-Compatible
4-A/4-A
UCC27517DBV SOT-23 5 pin (low voltage, independent -40°C to 140°C
(Symmetrical Drive)
of VDD bias voltage)
(1) For the most current package and ordering information, see Package Option Addendum at the end of this document.
(2) All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be
compatible with either lead free or Sn/Pb soldering operations. DRS package is rated MSL level 2.
Table 1. UCC2751x Product Family Summary
PART NUMBER PACKAGE PEAK CURRENT INPUT THRESHOLD LOGIC
(SOURCE/SINK)
UCC27511DBV
(1)
SOT-23, 6 pin 4-A/8-A CMOS/TTL-Compatible
(Asymmetrical Drive) (low voltage, independent of VDD
UCC27512DRS
(1)
3 mm x 3 mm WSON, 6 pin
bias voltage)
UCC27516DRS 3 mm x 3 mm WSON, 6 pin 4-A/4-A
(Symmetrical Drive)
UCC27517DBV SOT-23, 5 pin
UCC27518DBV
(1)
SOT-23, 5 pin CMOS
(follows VDD bias voltage)
UCC27519DBV
(1)
SOT-23, 5 pin
(1) Visit www.ti.com for the latest product datasheet.
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