Datasheet

UCC27511
UCC27512
www.ti.com SLUSAW9E –FEBRUARY 2012–REVISED DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage range, VDD 4.5 12 18 V
Operating junction temperature range -40 140 °C
Input voltage, IN+ and IN- 0 18 V
THERMAL INFORMATION
UCC27511 UCC27512
THERMAL METRIC SOT-23 (DBV)
(1)
WSON UNITS
6 PINS 6 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
217.8 85.6
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
97.6 100.1
θ
JB
Junction-to-board thermal resistance
(4)
72.2 58.6
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
8.6 7.5
ψ
JB
Junction-to-board characterization parameter
(6)
71.6 58.7
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
n/a 23.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
NOTE
Under identical power dissipation conditions, the DRS package will allow to maintain a
lower die temperature than the DBV. θ
JA
metric should be used for comparison of power
dissipation capability between different packages (Refer to the APPLICATION
INFORMATION Section).
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: UCC27511 UCC27512