Datasheet

UCC27511
UCC27512
www.ti.com SLUSAW9E –FEBRUARY 2012–REVISED DECEMBER 2013
Input Stage
The input pins of the UCC27511 and UCC27512 devices are based on a TTL/CMOS compatible input-threshold
logic that is independent of the VDD supply voltage. With typically high threshold = 2.2 V and typically low
threshold = 1.2 V, the logic-level thresholds can be conveniently driven with PWM control signals derived from
3.3-V and 5-V digital-power controllers. Wider hysteresis (typ 1 V) offers enhanced noise immunity compared to
traditional TTL-logic implementations, where the hysteresis is typically less than 0.5 V. These devices also
feature tight control of the input-pin threshold-voltage levels which eases system design considerations and
ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and
increases switching speed.
The device features an important safety function wherein, whenever any of the input pins are in a floating
condition, the output of the respective channel is held in the low state. This is achieved using VDD-pullup
resistors on all the inverting inputs (IN- pin) or GND-pulldown resistors on all the non-inverting input pins (IN+
pin), (refer to DEVICE INFORMATION for the device Block Diagram).
The device also features a dual-input configuration with two input pins available to control the state of the output.
The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin
(IN-). The state of the output pin is dependent on the bias on both the IN+ and IN- pins. Refer to the input/output
logic truth table (Table 5) and the Typical Application Diagrams, (Figure 19 and Figure 20), for additional
clarification.
When an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly
biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating
condition because whenever any input pin is left in a floating condition the output is disabled for safety purposes.
Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as explained
below.
• In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In
this case, the unused input pin, IN-, must be biased low (such as tied to GND) in order to enable the output.
– Alternately, the IN- pin is used to implement the enable/disable function using an external logic signal.
OUT is disabled when IN- is biased high and OUT is enabled when IN- is biased low.
• In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN- pin. In this
case, the unused input pin, IN+, must be biased high (such as tied to VDD) in order to enable the output.
– Alternately, the IN+ pin is used to implement the enable/disable function using an external logic signal.
OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
• Finally, note that the output pin can be driven into a high state ONLY when IN+ pin is biased high and IN-
input is biased low.
The input stage of the driver is preferably driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a mechanical socket or PCB layout is not optimal:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. The
differential voltage between input pins and GND is modified and triggers an unintended change of output
state because of fast 13-ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage.
• 1-V input-threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
• In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1
nF) between input pin and ground very close to the driver device may be necessary which helps to convert
the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid
unintended change of output state.
If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly
recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate-driver device package and transferring it into the external resistor.
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