Datasheet

VDD ThresholdVDD
IN+
OUT
IN -
VDD ThresholdVDD
IN+
OUT
IN -
VDD Threshold
IN-
OUT
IN+
VDD Threshold
IN-
OUT
IN+
UCC27511
UCC27512
SLUSAW9E –FEBRUARY 2012–REVISED DECEMBER 2013 www.ti.com
VDD and Undervoltage Lockout
The UCC2751X devices have internal Undervoltage LockOut (UVLO) protection feature on the VDD pin supply
circuit blocks. Whenever the driver is in UVLO condition (for example when V
DD
voltage less than V
ON
during
power up and when V
DD
voltage is less than V
OFF
during power down), this circuit holds all outputs LOW,
regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis
prevents chatter when low V
DD
supply voltages have noise from the power supply and also when there are
droops in the VDD bias voltage when the system commences switching and there is a sudden increase in I
DD
.
The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN wide band-gap power-semiconductor devices.
For example, at power up, the UCC2751X driver output remains LOW until the V
DD
voltage reaches the UVLO
threshold. The magnitude of the OUT signal rises with V
DD
until steady-state V
DD
is reached. In the non-inverting
operation (PWM signal applied to IN+ pin) shown in Figure 21, the output remains LOW until the UVLO threshold
is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN-
pin) shown in Figure 22 the output remains LOW until the UVLO threshold is reached, and then the output is out-
phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that
in these devices the output turns to high state only if IN+ pin is high and IN- pin is low after the UVLO threshold
is reached.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD-bypass capacitors are recommended to prevent noise problems. The use of surface-
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR
should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by
the load. The parallel combination of capacitors should present a low impedance characteristic for the expected
current levels and switching frequencies in the application.
Figure 21. Power-Up (Non-Inverting Drive) Figure 22. Power-Up (Inverting Drive)
Operating Supply Current
The UCC27511 and UCC27512 feature very low quiescent I
DD
currents. The typical operating-supply current in
Undervoltage LockOut (UVLO) state and fully-on state (under static and switching conditions) are summarized in
Figure 5, Figure 6 and Figure 7. The I
DD
current when the device is fully on and outputs are in a static state (DC
high or DC low, refer Figure 7) represents lowest quiescent I
DD
current when all the internal logic circuits of the
device are fully operational. The total supply current is the sum of the quiescent I
DD
current, the average I
OUT
current due to switching, and finally any current related to pullup resistors on the unused input pin. For example,
when the inverting input pin is pulled low additional current is drawn from VDD supply through the pullup
resistors (refer to DEVICE INFORMATION for the device Block Diagram). Knowing the operating frequency (f
SW
)
and the MOSFET gate (Q
G
) charge at the drive voltage being used, the average I
OUT
current can be calculated
as product of Q
G
and f
SW
.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias
voltages under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation
with theoretical value of average I
OUT
indicates negligible shoot-through inside the gate-driver device attesting to
its high-speed characteristics.
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