Datasheet

UCC27323-Q1, UCC27324-Q1, UCC27325-Q1
SLUS678A –MARCH 2008–REVISED APRIL 2012 www.ti.com
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by:
P = 2 × ½CV
2
f
Where f is the switching frequency
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With V
DD
= 12 V, C
LOAD
= 10 nF, and f = 300 kHz, the power loss can be calculated as:
P = 10 nF × (12)
2
× (300 kHz) = 0.432 W
With a 12-V supply, this equates to a current of:
I = P / V = 0.432 W / 12 V = 0.036 A
The actual current measured from the supply was 0.037 A, which is very close to the predicted value. But, the
I
DD
current that is due to the internal consumption should be considered. With no load, the current draw is
0.0027 A. Under this condition, the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high-frequency switching spikes and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to the
expected value.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the on and off states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Q
g
, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Q
g
= CeffV to provide the following equation for
power:
P = C × V
2
× f = Q
g
× f
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. For a power driver to be useful over a particular temperature range, the package
must allow for the efficient removal of the heat produced while keeping the junction temperature within rated
limits. The UCC2732x family of drivers is available in three different packages to cover a range of application
requirements.
As shown in Power Dissipation Ratings, the SOIC-8 (D) and PDIP-8 (P) packages have power ratings of
approximately 0.5 W at T
A
= 70°C. This limit is imposed in conjunction with the power derating factor also given
in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12-V V
DD
,
switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.
The MSOP PowerPAD™ package (DGN) significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in Reference 2, the PowerPAD packages offer
a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the package, reducing the θ
JC
to 4.75°C/W. Data is presented in Reference 2 to show
that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard
packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal
subsystem, as summarized in Reference 3. This allows a significant improvement in heatsink capability over that
available in the D or P packages and is shown to more than double the power capability of the D and P
packages.
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